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Flash Process Samsung 14nm Samsung 14nm aSLC mode
Series PHANES-EA PHANES-EA
Picture
Capacity 8GB, 16GB 4GB, 8GB
Package 153 Ball FFBGA(TFFBGA) Package 153 Ball FFBGA(TFFBGA) Package
Compatibility eMMC Specification Ver.4.4~5.1 eMMC Specification Ver.4.4~5.1
Bus mode - High-speed eMMC protocol.
- Clock frequency: 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
- High-speed eMMC protocol.
- Clock frequency: 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
3 data bus widths - Single data rate : up to 200Mbyte/s @ 200MHz
- Dual data rate : up to 400Mbyte/s @ 200MHz
- 8 parallel data rate : up to 52Mbyte/s @ 52 MHz (Default)
- Single data rate : up to 200Mbyte/s @ 200MHz
- Dual data rate : up to 400Mbyte/s @ 200MHz
- 8 parallel data rate : up to 52Mbyte/s @ 52 MHz (Default)
Operating temp.
(STD.Grade)
S : 0˚C~+85˚C S : 0˚C~+85˚C
Power requirement - Core Voltage (VCC): 2.7-3.6V
- I/O (VCCQ) Voltage: 1.7-1.95V/2.7-3.6V
- Core Voltage (VCC): 2.7-3.6V
- I/O (VCCQ) Voltage: 1.7-1.95V/2.7-3.6V
Weight (Max.) 2g 2g
Package Dimension(WxLxH,mm) 11.5 x 13.0 x 1.0 (mm) 11.5 x 13.0 x 1.0 (mm)
Warranty (Std./Ind.) MLC 2 years / Within 3K Erasing Counts aSLC Mode 2 years / Within 20K Erasing Counts
Flash Process Samsung 14nm
Series PHANES-EA
Picture
Capacity 8GB, 16GB
Package 153 Ball FFBGA(TFFBGA) Package
Compatibility eMMC Specification Ver.4.4~5.1
Bus mode - High-speed eMMC protocol.
- Clock frequency: 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
3 data bus widths - Single data rate : up to 200Mbyte/s @ 200MHz
- Dual data rate : up to 400Mbyte/s @ 200MHz
- 8 parallel data rate : up to 52Mbyte/s @ 52 MHz (Default)
Operating temp.
(STD.Grade)
S : 0˚C~+85˚C
Power requirement - Core Voltage (VCC): 2.7-3.6V
- I/O (VCCQ) Voltage: 1.7-1.95V/2.7-3.6V
Weight (Max.) 2g
Package Dimension(WxLxH,mm) 11.5 x 13.0 x 1.0 (mm)
Warranty (Std./Ind.) MLC 2 years / Within 3K Erasing Counts
Flash Process Samsung 14nm aSLC mode
Series PHANES-EA
Picture
Capacity 4GB, 8GB
Package 153 Ball FFBGA(TFFBGA) Package
Compatibility eMMC Specification Ver.4.4~5.1
Bus mode - High-speed eMMC protocol.
- Clock frequency: 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
3 data bus widths - Single data rate : up to 200Mbyte/s @ 200MHz
- Dual data rate : up to 400Mbyte/s @ 200MHz
- 8 parallel data rate : up to 52Mbyte/s @ 52 MHz (Default)
Operating temp.
(STD.Grade)
S : 0˚C~+85˚C
Power requirement - Core Voltage (VCC): 2.7-3.6V
- I/O (VCCQ) Voltage: 1.7-1.95V/2.7-3.6V
Weight (Max.) 2g
Package Dimension(WxLxH,mm) 11.5 x 13.0 x 1.0 (mm)
Warranty (Std./Ind.) aSLC Mode 2 years / Within 20K Erasing Counts
Flash Process Samsung 14nm Samsung 14nm aSLC mode
Series PHANES-EA PHANES-EA
Picture
SpecSheet N/A N/A
DataSheet Downloads Downloads
Dimension See Datasheet See Datasheet
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